Tuesday, 2013-03-26

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dvhartprpplague, poke,we're on16:08
prpplaguedvhart: ??16:09
dvhartprpplague, pm16:10
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dvhartprpplague, can you provide an example of a Linux kernel driver using the hw rst on the AR8031?21:31
dvhartprpplague, there are some timing requirements wrt the clock and I'd like to see an example if there is one already out there.21:31
dvhartI have a prototype of the PCI Sub ID bits in place21:32
prpplaguedvhart: yea, can i get back to you on this, trying to get the pcb fabs ready21:35
prpplaguedvhart: they are all arm21:35
dvhartprpplague, I figured. I'm looking, but I suspect they may be external to mainline21:36
dvhartthe PAL phy driver doesn't seem to have a hw reset routine21:36
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mranostaydvhart: using the pci quirks?22:39
dvhartmranostay, currently just pci sub id22:40
mranostayhack alert!22:41
mranostay:)22:41
dvhartswitch (pdev->subsystem_device_id)22:41
dvhartoh yeah, still under dev22:41
dvhartso yeah, lots of hacking going on22:41
dvhart(although I'm not sure this particular thing is an ugly hack... rather clean actually)22:41
dvhartthe ugly bit is pch_gbe_phy.c :-(22:42
mranostaybe sure to post that patch so we can give advice :) *evin grins*22:42
dvhartsomething like PAL seems great... but the driver implementations are so sparse :/22:42
dvhartI'll post when I'm either stuck or have something I think is worth presenting22:43
dvhartright now it isn't worth looking at22:43
mranostaydvhart: this for the PHY reset?22:43
dvhart(you can if you want to, but it is going to change so much)22:43
dvhartmranostay, 3 things22:43
dvhart1) read MAC from nvram (or similar)22:43
dvhart2) PHY reset with GPIO 1122:44
dvhart3) Set TX Clock Delay in PHY22:44
dvhart#2 is the ugliest22:44
dvhartand isn't fully implemented22:44
dvhartas that requires so much board specific knowledge22:44
dvhartin a driver that had zero provisioning for even using a different phy22:44
dvhartI need some context from the original author, so I'm going to get some info out to them today22:45
mranostayuse a rubber hose it doesn't leave marks22:46
dvhartheh22:47
mranostayyeah i can see #2 being ugly22:47
dvhartThe Intel designs to date all use the same phy, gpios, etc22:47
dvhartso this is stretching the flexibility of the drivers, understandably so22:47
dvhartso finding the optimal path is most of the work22:47
dvhartnone of the code is actually hard :)22:48
mranostaywhat you don't want is a Minnowboard only kernel :)22:48
dvhartexactly22:48
dvhartthat isn't acceptable22:48
dvhartFedora ARM "support" for example.... need to avoid that kind of thing.22:48
mranostayheh22:49
mranostaydvhart: anything else on the minnowboard need an erranum in software?22:50
mranostaydriver level i mean22:50
dvhartthe pch_uart driver has multiple clocks that the firmware sets up22:51
dvhartso a simple switch in there to pick the right one22:51
dvhartwhich is consistent with the features I added to that driver a year ago in support of the FRI2 and another board22:51
dvhartso that's easy22:51
dvhartthe gpio_sch driver had a bug I've submitted a fix for22:52
dvharttwice and is still sitting actually, time to email gregkh on that one22:52
dvhartbut that was a bug, not a quirk22:52
dvhartanother has already been merged22:52
dvhart(lpc_sch)22:52
dvhartthe platform driver is the tough one22:53
dvhartthe thing that sets up the GPIOs, buttons, and LEDS and the HWID22:53
mranostaydvhart: you didn't bribe^H^H^H^H^Hbuy him beer at the last conference? :)22:53
dvhartit's easy to write a platform driver, but I'm trying to do it with an ACPI SSDT, and that's fairly new ground. Fortunatley I'm tight with the ACPI people ;-)22:53
dvhartheh, I used to work with Greg, I don't have any trouble getting patches in to him :)22:54
dvhartI just didn't Cc him before, hoping the driver maintainers would have managed it for him22:54
dvhartI try not to add to his INBOX if I can avoid it22:54
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mranostayTartarus: we let you in here?23:40

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