Friday, 2014-10-03

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newb_hi, anyone home?00:44
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GPSFanprpplague, ping no, was out of town all day, just got back... I can't find anything newer than may or june. I'm probably looking in the wrong spot... ;>P00:47
prpplagueGPSFan: the pdf schematics should be up to date00:50
prpplagueGPSFan: i just pushed them00:51
* prpplague double checks00:51
prpplagueGPSFan: you can also check out the github where everything is anyway -
prpplagueGPSFan: were you look at phase1 or phase2 designs?00:52
prpplagueGPSFan: maybe join #retro-computing  when you have a minute00:52
GPSFanprpplague, you said phase 200:52
prpplagueGPSFan: ahh00:52
prpplagueGPSFan: yea, i haven't gotten everything complete for phase2 yet, so00:53
prpplagueGPSFan: sorry00:53
prpplagueGPSFan: as tired as i been lately, i must have misunderstood your question00:53
prpplagueGPSFan: do you remember what issue/question you had on phase2 blocks?00:54
GPSFanprpplague, on worries, you had said phase 2 and I could only find phase 1. I'll have to look again. I'll use the github00:55
prpplagueGPSFan: yep, the files are up on github00:55
GPSFanbeen a long day00:55
prpplagueGPSFan: no worries old friend00:55
prpplagueGPSFan: it certainly has been00:55
GPSFanfor some definition of old ;>))00:56
prpplagueGPSFan: hehe01:00
GPSFanprpplague, I guess the big issue I had with both phase 1 & 2 is using the TC output of the hc160 (pin 15) as a clock. IIRC even though the internal counter is synchronous, the TC output can glitch, thereby clocking the following circuit improperly.01:11
prpplagueGPSFan: yea, i found that out afterwards01:12
prpplagueGPSFan: i fixed it up as a master/slave flip flop01:12
prpplagueGPSFan: to address the issue01:12
prpplagueGPSFan: phase2 updated01:12
prpplagueGPSFan: the phase1 schematics are updated as well to reflect the white wire fixes01:13
prpplagueGPSFan: i was really really trying to emulate exactly what was in the witch schematics as close as possible01:14
prpplagueGPSFan: with one exception01:15
prpplagueGPSFan: they had two clock inputs to drive the steps for the dekatrons01:15
prpplagueGPSFan: which handled the glitch01:15
prpplagueGPSFan: so when i duplicated it without the dual clocks, i was so focused on the core , that i missed that01:15
GPSFanI gotta go eat something, I'still having trouble telling one of those pdf's from the other.01:16
prpplagueGPSFan: ok, let me know when you get back, i want to figure out how to make it easier to follow01:16
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GPSFanprpplague, back. I must have cloned before you pushed up to github. I just pulled and the phase 2 a & b now match what is on the wiki.01:57
prpplagueGPSFan: dandy01:59
prpplagueGPSFan: so that is the document i am working through02:00
GPSFanin phase 2 you are still clocking the jk ff from the TC output. ie. (IC7-15(TC) goes to IC9a-1 (CK) IMHO I think it should be a 7474 vs 7473 and the TC should go to the D input with the clock of the 7474's going to something that chocks the TC values after they had time to settle.02:03
prpplagueGPSFan: yea basically i'm using it in a master-slave configuration02:04
* prpplague makes notes of your suggestions 02:05
prpplagueGPSFan: let look02:05
GPSFanyes, but the clock still can be glitchy, as in it may falsly transition to a 1 while the final proper state is 002:05
prpplagueGPSFan: hmm02:07
prpplagueGPSFan: i'd have to see a timing diagram example02:07
GPSFanok, I'll gen something up tomorrow.02:07
prpplagueGPSFan: i thought i had taken care of that by using the dual jk's together with the AND gate02:07
prpplagueGPSFan: basically that is what i am replicating in phase102:08
GPSFanbut the clock of the jk is still edge triggered so if you get an errant edge you will clock the ff when you don't want to.02:09
prpplagueGPSFan: ahh right, so you are saying if there is noise/glitch on the signal it would trigger the transition02:10
GPSFanyes, so the tc output really should go true after 10 clocks to the hc160 input, but sometimes during the countup, the tc will go true and false again very quickly... a glitch which doesn't represent the proper final state of the count.02:13
prpplagueGPSFan: ok, one additional item, the logic is done so that the TC is actually valid of the value of zero, not on 902:13
GPSFanthis is alot mor prevalent when the counter is a ripple (async) counter vs sync.02:13
prpplagueGPSFan: ahh right02:13
prpplagueGPSFan: i hadn't seen any indications of that on the scope on LA while doing my original testing02:14
GPSFanbut I've seen it happen in sync counters too02:14
prpplagueGPSFan: my only issue was getting the transitions to occur on the clock edges02:14
GPSFanonce you get to having 10k units in the field (74hc160's) you will see all sorts of varients.02:14
prpplagueGPSFan: i would imagine so02:15
GPSFanprocess variations and maybe one counter stage is a bit slower than the rest. all clocked at once the outputs change except for the slow one maybe 20ns different, and you have a 20ns glitch.02:17
prpplagueGPSFan: ok, i'll go back and have a look at using 7474 series02:17
prpplagueGPSFan: that'll set be back some, but probably save time in the long run02:18
GPSFantalk tomorrow, my eyes are crossing out of control, and I didn't have that much beer... ;>P02:18
prpplagueGPSFan: just fyi that is the timing i am trying to replicate02:19
prpplagueGPSFan: laters02:19
GPSFanah, that will help, thanks02:21
GPSFanprpplague, in the timing diag, where are the transfer pulses that connect to the cath of V2?02:27
GPSFanand the pulsed 70V supply?02:28
prpplagueGPSFan: in this example the transfer pulses are the same as the 10A pulses in the diagram02:29
prpplagueGPSFan: the pulsed 70V is basically the reset02:30
prpplagueGPSFan: it's pulsed at the start of a new transfer to reset it to the start condition02:30
GPSFanok, and v1 is not one of the decatron tubes but something else.02:31
prpplagueGPSFan: correct02:32
prpplagueGPSFan: it's acting like the based JK i have configured02:32
prpplagueGPSFan: basically it has a low value until it is clocked once, then it remains high until reset02:32
prpplagueGPSFan: C is the input to V1, and D is the output02:33
prpplagueGPSFan: maybe we should jump over to #retro-computing before warthog9 get's mad...02:34
* prpplague invites GPSFan to join #retro-computing02:34
GPSFanyep. in the timing example it takes 14 pulses (7 G1 and 7 G2) to get anoutput from ZC02:35
* prpplague looks02:35
GPSFanpulses being active low (-60v)02:36
prpplagueGPSFan: yes that is correct02:36
prpplagueGPSFan: in this example a value of 7 is stored in the first dekatron02:36
GPSFanah, how large a # can be stored in a single decatron?02:37
GPSFanand thos pulses are counting it (whatever it is) down to 0.02:37
prpplagueGPSFan: dek = 1002:38
prpplagueGPSFan: so a dekatron has the zc on zero02:38
prpplagueGPSFan: where as the counter i have has the zc on 902:38
GPSFanso how come the 14?02:38
prpplagueGPSFan: hehe02:39
prpplagueGPSFan: you have to do a two pushes in order to increment02:40
prpplagueGPSFan: or in opposite sequence to decrement02:40
prpplagueGPSFan: since that isn't required for the counter i have, 10B pulses are not implemented02:40
GPSFanah, an up/down counter02:41
prpplagueGPSFan: right02:41
prpplagueGPSFan: only thing is, you only can know if it is zero , or not02:42
GPSFanunless your operator looks at the face of the tube.02:42
* GPSFan is getting punchy02:43
prpplagueGPSFan: indeed, but even then, it is pretty difficult02:43
prpplagueGPSFan: hehe no worries02:43
prpplagueGPSFan: we can carry on later02:43
prpplagueGPSFan: just excited that someone else has taken an interest in the project02:43
GPSFanindeed, cul02:43
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prpplagueGPSFan: laters02:44
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Bhaalprpplague: Hope you are well, It's been a little while since I pestered you :)03:16
BhaalGot an idea of when Mouser might have a stock level of MMaxs?03:16
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shoe_hatIs Minnowboard powerful enough to play hd movies with vlc?03:41
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tbrshoe_hat: if vlc can use the intel hw acceleration, then for sure06:02
tbrif you look around you'll find examples of multiple fullHD files being played back in parallel06:03
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hrwiirc someone posted 4 2K videos at same time10:22
RzR has same pict twice14:26
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calculustwice, you mean there is the same for th 6-pin and 4-pin options?14:42
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jake_hi all, on the Minnowboard Max, is it possible to supply power to the board through the Low-Speed Header? Ex. just an external 5V to pin 3?16:05
prpplaguejake_: yes it is16:07
jake_nice, I just wanted to be sure, because there is not a direct electrical connection between the pin on the barrel jack and the pin on that connector16:09
prpplaguejake_: right, that pin is after the protection circuitty16:14
prpplaguejake_: so if you do power it from there, you will need to be careful to provide the correct current, and voltage16:15
jake_aha, makes sense, better that then a little barrel connector dongle from the top board to the bottom tho :)16:15
jake_thanks again!16:29
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RzRwarthog9, printed the case16:32
RzRwarthog9, will file bug before patches16:32
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warthog9RzR: cool, I know there's a bug in the serial cable hole placement23:26
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