Tuesday, 2016-12-20

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warthog9well that upgrade to Fedora 25 could have gone better01:00
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bluelightningwarthog9: from 24 or 23?01:39
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warthog9bluelightning: I did a jump from 23 to 2505:44
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bluelightningwarthog9: I have to do the same - what happened?06:41
warthog9some mess with X to wayland06:42
warthog9and active directory06:42
warthog9otherwise it was surprisingly straight forward06:42
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BitweasilMorning!16:43
warthog9morning Bitweasil16:44
BitweasilSo, yeah, reading config space works better when you write the address and read the data port, instead of just setting the data to the address you wanted to read...16:44
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zentrumBitweasil: what you are doing with PCI?18:31
Bitweasilzentrum, enumerating it.18:34
BitweasilNot the first time I've written code to do that.  I can't *quite* bang it all out from memory. :)18:41
BitweasilOf course, then I go and do silly stuff like for(UINT16 i = 0; i < 65536; i++) and wonder why it never terminates. ;)18:51
bluelightningheh18:53
Bitweasil"Jokes I don't tell locally because nobody would get them."18:58
Bitweasilwarthog9, if you want to change default settings for the EFI config with a new EFI image build, you can change things in places like Vlv2TbltDevicePkg/PlatformSetupDxe/SouthClusterConfig.vfi - move the DEFAULT flag to what you want the new default to be, and it'll work.19:03
Bitweasil(for, say, making LPSS & SCC Devices Mode default to PCI Mode)19:03
warthog9Bitweasil: hehe19:05
warthog9yeah I know we flipped it to it's current default for Microsoft, so we likely won't be flipping it back19:05
BitweasilWhat does Microsoft have against PCI config space?19:05
warthog9they prefer ACPI on Windows19:06
BitweasilI don't care, just figured I'd mention it, since you weren't sure how to change setup defaults when I asked a few days ago.19:06
* Bitweasil goes to light the generator.19:06
BitweasilAlrighty, let him warm up for a bit before I ask for much...19:08
warthog9Bitweasil: ahhh good to know on the defaults19:09
BitweasilYeah, I just moved the DEFAULT flag over and it did what I want.19:09
warthog9:-)19:10
BitweasilFigured I'd mention it.19:11
BitweasilYou can update the wiki for the EFI hackers if you care.19:11
warthog9good to know19:11
warthog9I've been meaning to go dig through the menus and rearrange them anyway19:11
warthog9as the way they are laid out only makes sense to the very low level hardware / firmware people that I know of19:11
BitweasilHeh.  It took me a while to find what I was looking for.19:16
BitweasilIs Vlv2TbltDevicePkg just for the Minnowboards, or is that more general?19:16
warthog9was brought in because of minnow19:17
BitweasilOk.  It seemed awfully minnowboard specific.19:17
warthog9yeah, it more or less is minnow19:17
BitweasilSo nice having the source for the whole thing...19:20
BitweasilOr, at least, most of it.19:20
warthog9as much as I could get so far19:21
BitweasilI'd love to peek inside the bringup code at some point, but I expect that's either orange or red...19:21
warthog9pretty sure that's red19:21
BitweasilThat wouldn't surprise me a bit.  Kind of what I assumed, though I don't actually understand why it's considered secret sauce.19:21
warthog9on the plus side the firmware team we are working with is pretty keen on open source as well at this point, so we've got a solid ally on that front19:22
BitweasilExcellent.  I don't like binary blobs...19:22
BitweasilOf course, if you don't trust Intel to be non-malicious, open source bringup code on their hardware doesn't really help, but, still.19:23
BitweasilI expect part of it is because it's tickling non-public interfaces.19:23
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zentrumBitweasil: im about to extend the pci implementation of minix3 to pcie19:39
BitweasilMinix3?  Unfamiliar.  I don't do the hardware side of it, just the software side.19:39
BitweasilI spend a lot of time in weird corners of Ring 0.19:39
zentrumhad to make acpi working before19:39
BitweasilYeah, I just switched them to PCI mode so I could read the BARs like a normal human...19:39
zentrumBitweasil: minix3 is software (its OS) ;)19:40
zentrumim doing acpi only for the ECM19:40
zentrumthe basic 256 bytes pci config space are still there19:40
BitweasilEew.  ACPI parsers are messy. :p19:41
warthog9Bitweasil: minix3 is Tanenbaum's favorite OS19:41
zentrumbut the 4k ECM are pretty nice but you'll need SMBus too, otherwise most of the pci e devices make no sense19:41
zentrumBitweasil: minix3 uses the acpica19:41
BitweasilMinix!19:42
BitweasilI was parsing it as Mini X319:42
BitweasilWhich sounded like some similar embedded board.19:42
zentrumyou should rewrite your parser ;)19:42
warthog9Bitweasil: it's a VERY small car ;-)19:42
BitweasilEh, I'll just hardcode stuff if I have to mess with ACPI.  All I really want is the HS UARTs working from ring 0 code...19:43
BitweasilSo I can dump debug output at a good clip.19:43
zentrumwarthog9: we are about to implement the framebuffer as well, minix3 runs natively on a stock minnowboard with 32 bit efi19:43
Bitweasil115200 is glacial, 3M baud is better. ;)19:43
zentrumBitweasil: HSUART is ugly as well :)19:46
zentrumi would bet half of my grey hairs coming from UART handling and minnowboard :)19:47
zentrumtoook quite long to find out the legacy uart wired only GND, RX and TX, no RTS, no CTS...19:47
zentrumin the meanwhile its documented19:48
BitweasilAny advice?  My plan is to stick it in polled FIFO mode and bang out characters while FIFO not full.19:48
BitweasilBasically the same as a normal UART, just a different interface.19:48
zentrumsimply a pci uart19:48
Bitweasilwhile (uart_is_full()); uart_data = byte;19:48
Bitweasiletc.19:48
BitweasilI've only dealt with 3f8 UARTs so far.19:49
BitweasilBut it looks like once you've got the BAR and configured things, you can treat it similarly.  Just faster.19:49
zentrumno big difference, instead of writing to ports (PBIO) you will write to memory (MMIO)19:49
BitweasilYeah.19:50
BitweasilThat's what it seemed like reading the e3800 manual.19:50
zentrumyepp, the baytrail doc is quite good to a certrain degree19:50
BitweasilOnce you learn how to parse Intel docs, they're pretty solid.  Not easy reading, but fun. :)19:51
BitweasilAnd an awful lot of "Oooh, reserved bits!  *poke those and see what happens*" going on. :)19:51
zentrumbasically, i would prefer some machine readable docs at all19:51
zentrumwould be perfect to have something like that, because then you can decide how to generate your header file and macros...19:53
zentrummaybe I should start a github project for that...19:53
BitweasilYou have more time than I do. :p19:53
BitweasilQ: For high speed UART stuff, should I bother with flow control?  Or is that just going to mess me up in the long run?19:55
zentrumBitweasil: basically, i would make it work first without flow control, but i would implement it after having it work19:56
Bitweasilok19:57
zentrumi did not look into detail how they work with IRQs and buffers there...19:58
BitweasilI'm not doing anything interrupt driven - just the FIFOs.19:58
zentrum.oO[ damn, just remember to fix the broken local apic and msi-x in minix as well ]19:59
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BitweasilOnce you enable CTS/RTS support, it should be handled by the hardware, though.20:07
BitweasilAll I'd have to do is add a timeout in the write loop to prevent a CPU from hanging if CTS isn't asserted.20:07
BitweasilI think.20:07
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Bitweasilwarthog9, question:  The HSUART doc says it supports up to a 64 character FIFO, but the default is 16, the transmit/receive level registers are only 5 bits long, and I can't see where the depth is set.  :)  What's the actual depth, and if it's greater than 16, how do you set that?21:50
warthog9Bitweasil: asking all the hard questions21:52
Bitweasil27.6.40, Component Parameter Register, bits 23:16 look like they might be relevant, but I'm not sure.21:53
BitweasilAnd it goes well beyond the claimed 64 character FIFO size.21:54
BitweasilFIFO_MODE21:54
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warthog9I'm still reading up in 24.321:57
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BitweasilAh, the CH#_FIFO_DEPTH stuff?21:59
warthog9sorry got distracted, that sounds promising though22:00
Bitweasilnp.  Those look like RO fields, though.22:00
warthog9Bitweasil: do you have table 282?22:01
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BitweasilYes, HSUART PCI config registers?22:02
warthog9TFL and RFL?22:02
warthog927.6.2922:03
BitweasilUh, I'm familiar with those, yeah.  Bits 4:0, marked RW22:03
warthog9"this indiciates the number of data entries in the transmit FIFO"22:03
BitweasilRight, I read that as the current number in the queue, not the raw depth.  Also, 5 bits isn't enough to encode 64 characters of data.22:04
BitweasilI suppose I can try writing them. :)22:04
warthog9dunno, that's my first lead22:04
BitweasilOk.  16 characters isn't the end of the world, just would be nice to be able to shove more data into the FIFO and go back to the OS.22:05
warthog9yeah22:05
warthog9Bitweasil: where did you see the 64 character fifo info?22:05
Bitweasil27.2.1, under (in mine) figure 127 - "Each UART has a Transmit FIFO and Receive FIFO and each holds 64 characters of data."22:06
warthog9yeah, just found that22:06
BitweasilAlright, I'll mess around.  Wasn't sure if you'd run across that or not.22:10
BitweasilApparently not. :)22:10
warthog9not that specific one22:10
warthog9though I'm digging through the documentation right now22:10
warthog9seeing if there's anything other thant tfl and rfl that jump out at me22:11
warthog9otherwise I'm just sitting here quickly doing up a minnowboard to rPi adapter22:11
BitweasilUh.  What sort of adapter?22:12
warthog9our 26 pin to their 40 pin22:12
warthog9so you could take an rpi thingie and hook it straight up22:13
BitweasilOh, bringing out the I2C and stuff in a compatible manner?22:13
warthog9yup22:13
BitweasilNeato!22:13
warthog9it's straight forward22:13
warthog9pretty sure I can make it work for most things without issue22:13
BitweasilYeah, 3.3V on the GPIO for both, IIRC22:14
warthog9that's what I read, but someone was telling me there needed to be some active component, and I haven't found anything that makes that obvious22:14
BitweasilI... can't see why.  You've already got the level shifters.22:14
warthog9so quick design, probably order pcbs and test ;-)22:15
warthog9I couldn't find anything obvious in any of the rPi shield designs that needed anything active22:15
BitweasilSounds like fun.  My last analysis involving level shifters involved discovering that the ESP8266 modules, while needing a 3.3V Vcc, are actually 5V tolerant on their GPIO, so you can bolt them straight up to an Arduino and be fine.22:15
BitweasilSo far, so good...22:16
warthog9that's useful22:16
warthog9I've got an esp8266 design I'm doing for pycon pune right now22:16
BitweasilYeah, really was.  3.3V is a logical 1 for a 5V system, and some people subjected the GPIOs to higher voltages with no increase in current measured.  Plus, the GPIOs are protected at around 6V with a clamp.22:16
BitweasilWhich... seems silly, if they're damaged at 5V.22:16
BitweasilSo I just bolted mine straight up and everything is fine so far.22:16
warthog9how longs it been running?22:17
BitweasilSix months on one of them.22:17
Bitweasilhttp://www.ba0sh1.com/2016/08/03/is-esp8266-io-really-5v-tolerant/22:19
BitweasilData seems to say it's OK.22:20
warthog9well if it hasn't melted, that's pretty good data :-)22:25
Bitweasil:)  Yeah.  Now I need to finish the rest of the damned project, which involves rewriting half a dozen Arduino libs to be "not stupid."22:25
warthog9Bitweasil: I should have my esp8266 design done tonight and ready to go22:29
warthog9Bitweasil: hehe22:29
warthog9yeah I'm going micropython so I'm way up a creek22:29
BitweasilI've designed my own Arduino shield for my project. :)  PCB design is fun.22:30
warthog9it's cathartic22:30
warthog9I've been doing the layout on mine for 3 days now22:30
BitweasilThis is the first one I've done, so it took me a few weeks to learn the tools.22:32
BitweasilAnd it was pretty simple.22:32
BitweasilNot exactly full time work either.22:33
BitweasilIs there any sort of fancy way to flash an EFI firmware over the network? :)22:58
BitweasilHeh.  (uint32_t *)base + offset != (uint32_t *)(base + offset)23:01
BitweasilBeen a bit since I've been down in the weeds.  Scraping off some rust.23:01
warthog9Bitweasil: remember to take your liquid wrench23:05
Bitweasil:p23:10

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