Wednesday, 2017-07-05

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minnownoobI noticed that on the schematic for MEM_CHA-1 and MEM_CHA-2 there are connections from a pin that connects the CPU data pin to the DDR3 chip data pin such as M_DATA_XX to M_DATA_R_XX. What is the point of having M_DATA_R_? Why not just connect M_DATA_XX on the CPU schematic to M_DATA_XX on the DDR3 schematic without this "R" intermediary.13:33
minnownoobIs this just something necessary for off page connections in the software? For me in Altium I can just make off page connections directly since the connection is global. Not sure what software the Minnow used.13:34
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minnownoobI noticed that on the schematic for MEM_CHA-1 and MEM_CHA-2 there are connections from a pin that connects the CPU data pin to the DDR3 chip data pin such as M_DATA_XX to M_DATA_R_XX. What is the point of having M_DATA_R_? Why not just connect M_DATA_XX on the CPU schematic to M_DATA_XX on the DDR3 schematic without this "R" intermediary.15:14
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minnownoobWhat is the best place to get questions answered regarding Minnowboard schematics?17:05
BitweasilI don't think anyone here was involved in the design of it.17:06
BitweasilAt least not at that level.17:06
BitweasilThe _R_ pin may be a test point for development?17:06
BitweasilI'm not sure.17:06
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minnownoobOK. Thanks. Is there a forum or email list better suited for those questions?17:15
m_wminnownoob: what do you need to know?17:19
minnownoobThe reason why there is no direct connection between the RAM chip and the CPU. Physically I interpret it as a direct connection however I am not sure why they have this intermediary net of XXXX_R between pages.17:22
minnownoobFurthermore, I was glancing over the actual minnowboard vs the schematic and noticed many components missing that are in the schematic17:22
m_wwhich board do you have?17:23
minnownoobTurbot17:23
m_whttps://github.com/MinnowBoard-org/design-files/blob/master/minnowboard-turbot-dual-core/pcb-F400_R302_Turbot-B/Turbot_B_Dual_Core_F400_R302-SchematicRev200.pdf17:24
m_wdual core?17:24
minnownoobYup, that is the schematic I have17:24
minnownoobYes17:24
m_wokay17:24
minnownoobOn top of it, I see there are 0 ohm resistors. Not sure why those are necessary.17:25
m_wthese label are confusing17:26
Bitweasil0 ohm resistors are typically just jumpers for crossing over another trace.17:27
minnownoobAhhhh17:28
minnownoobMakes sense17:28
BitweasilI've also seen them used for manually toggling things with an iron, but probably not the case for this board.17:28
minnownoobOK17:29
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minnownoobOne last question that is bothering me is what exactly is the "swap circuit" which is referenced in the DDR3 portion of the schematic?17:35
m_wthat is a good question17:37
m_wI think that would explain the funky labelling17:37
minnownoobCan't find any reference to swap circuits anywhere. But you are right, the order of I/O in the swap circuit seems almost random. Outside of that swap circuit it is pretty uniform17:40
m_wminnownoob: I will see if I can find out what is going on there17:44
minnownoobGreat. Thanks!17:48
BitweasilIs it something related to trace length balancing or randomly mixing the signals for EM and power reasons?18:06
BitweasilThere's a lot of weird stuff related to memory on those fronts.18:06
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